1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of small circuit elements, such as a gate electrode of a field effect transistor, on a substrate, wherein the dimensions of the circuit elements are significantly less than the resolution of the involved lithography technique.
2. Description of the Related Art
The trend in recent years to steadily decrease the feature sizes of elements in micro-structures, such as circuit elements in integrated circuits, will continue in the near future, wherein reproducible and robust processes have to be established that allow the formation of a huge number of integrated circuits in a cost efficient manner. Presently, sophisticated integrated circuits that are available as mass products include elements having dimensions which are well below the optical resolution of the lithography apparatus used for transferring a pattern from a mask into a material layer formed on a substrate. Minimum dimensions of circuit elements are presently 100 nm and less, wherein the wavelength of radiation used for optically transferring patterns from the mask to the substrate surface is in the deep ultraviolet range at a wavelength of, e.g., 248 nm, and, according to recent developments, at approximately 193 nm. In this wavelength range, the absorption of optical transmissive elements, such as lenses, is considerable and will drastically increase with a further reduction of the wavelength. Thus, merely reducing the wavelength of light sources for lithography apparatus is not a straightforward development and may not easily be implemented in mass production of circuit elements having feature sizes of 50 nm and less.
The total resolution of reliably transferring circuit patterns from a mask to a substrate is determined, on the one hand, by the intrinsic optical resolution of the photolithography apparatus, the characteristics of materials involved in the photolithography patterning process, such as the photoresist and any anti-reflective coatings (ARC) that are provided to minimize deleterious scattering and standing wave effects in the photoresist, and by deposition and etch procedures involved in forming the resist and ARC layers and etching these layers after exposure. In particular, the highly non-linear behavior of the photoresist, in combination with sophisticated ARC layers and lithography mask techniques, allows the formation of resist patterns having dimensions considerably below the intrinsic optical resolution of the photolithography apparatus. Additionally, a further post-lithography trim etch process is applied to further reduce the feature sizes of the resist pattern that will serve as an etch mask in subsequent anisotropic steps for transferring the resist pattern into the underlying material layer. Thus, this resist trim process enables reduction of the critical dimension of the gate electrode to a size that is well beyond the wavelength of the photolithography.
It is, however, of great importance to accurately control the resist trim process so as to form a precisely defined mask for the subsequent anisotropic etch process for patterning the gate layer stack, since any variation of the gate length directly translates into a corresponding variation of operating speed of the final device.
With reference to FIGS. 1a–1c, a typical conventional process flow for forming a gate electrode of a field effect transistor including a control regime for the resist etch trim will now be described in more detail. FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 during an early stage of the fabrication of a line-like circuit element, such as the gate electrode of a field effect transistor. The semiconductor device 100 comprises a substrate 101, for instance a silicon substrate, or any other appropriate substrate with a suitable semiconductive layer formed thereon. A layer stack 102, for instance appropriately configured so as to enable the formation of a gate electrode, is formed on the substrate 101 and may include a gate insulation layer 103 and a gate material layer 104, such as a polysilicon layer. An anti-reflective coating 105 of appropriate thickness and material composition, for instance, comprised of silicon enriched silicon nitride, silicon oxynitride, and the like, is formed on the layer stack 102, followed by a resist mask feature 106 having an initial lateral size, which is referred to as Dinitial, wherein the lateral size Dinitial is oriented along a length direction, i.e., the horizontal direction in the plane of FIG. 1a, of a gate electrode to be formed from the layer stack 102.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. First, the layer stack 102 is formed, for instance by forming the gate insulation layer 103 using advanced oxidation and/or deposition methods as are well known in the art. Subsequently, the polysilicon layer 104 may be deposited by chemical vapor deposition (CVD), followed by the deposition of the anti-reflective layer 105, the thickness and a material composition of which are selected so as to significantly reduce a back reflection of radiation during a subsequent lithography process. The thickness may typically range from 30-150 nm for a silicon rich nitride layer that may be formed by thermal CVD, plasma enhanced CVD, and the like, while controlling the material composition during the deposition process. Next, a resist layer comprised of a deep UV-sensitive material is deposited, for instance by spin-on techniques, and is subsequently exposed to a deep UV radiation having a wavelength of, for example, 248 nm or 193 nm. After development of the resist layer, including any well-known pre- and post-development procedures such as baking and the like, the resist mask feature 106 is formed having the lateral dimension Dinitial, which may be significantly greater than a desired gate length Dtarget of the gate electrode still to be formed. As previously explained, even for a highly non-linear behavior of the photoresist used, the lateral size Dinitial of the resist mask feature 106 still significantly exceeds the required target value by about 30–50%, especially as the critical feature size Dtarget is on the order of 100 nm and significantly less. For this reason, the etch process for forming the gate electrode includes a first step for reducing the size of the resist mask feature 106 in a well-controlled manner prior to etching the anti-reflective coating 105 and the polysilicon layer 104 by using the resist mask feature 106 having the reduced size as an etch mask. To this end, an appropriately selected etch chemistry is provided in a gate etch tool, wherein the material removal of the resist mask feature 106, i.e., the reduction of the lateral size Dinitial and of course of the height of the resist mask feature 106, may depend substantially linearly on the etch time for a plurality of available resists. Hence, the etch time of the resist trim process may be calculated in advance on the basis of a linear model requiring as input parameter values of the lateral size Dinitial and the desired critical dimension Dtarget. The required etch time for the resist trim process may therefore be calculated on the basis of the following equation:Dtarget=Dinitial−a·t−c,wherein the coefficients a and c may be determined from a corresponding trim curve relating the etch time to the material removal of the resist for a plurality of test substrates that have been processed by the gate etch tool operated by a specified resist trim recipe.
FIG. 1b schematically shows the semiconductor device 100 after completion of the resist trim process, wherein the lateral size Dinitial is reduced by the amount of 2·ΔD, wherein ΔD may be controlled by accordingly adjusting the etch time to the value obtained by the model explained above. Hence, a resist mask feature 106A is formed having a lateral size that substantially corresponds to the desired critical dimension Dtarget, wherein a deviation from this target value depends on the linear trim etch model and the uniformity of the gate etch tool over time. Thereafter, the reactive atmosphere in the gate etch chamber is correspondingly altered so as to provide a highly anisotropic etch ambient that enables the etching of the anti-reflective coating 105 and the polysilicon layer 104, wherein a high selectivity to the gate insulation layer 103 is required so as to not unduly damage the underlying substrate 101 when the etch front stops within the thin gate insulation layer 103.
FIG. 1c schematically shows the semiconductor device 100 after the completion of the anisotropic etch process, thereby forming a gate electrode 104A, while the residue 105A of the anti-reflective coating 105 and the residue of the resist mask feature 106A cover the top surface of the gate electrode 104A. The lateral dimension of the gate electrode 104A, i.e., the gate length, is denoted as Dfinal, which should substantially conform to the desired critical dimension Dtarget, as any significant deviation therefrom would lead to a significantly changed device performance. In highly sophisticated integrated circuits, the desired critical dimension of the gate length may be significantly less than 100 nm with a tolerance of ±1 nm.
In the conventional process flow as described above, the feed forward strategy, i.e., the measurement of the initial lateral size of the resist mask feature 106 as produced by the lithography process and the respective calculation of the etch time of the resist trim process for a substrate to be subsequently processed, is based on the assumption that all relevant variations of previously performed process steps that affect the gate etch process are sufficiently taken account of by the measurement value Dinitial. Upon further device scaling, however, it turns out that it is extremely difficult to maintain the deviations of the gate length Dfinal with respect to the target value Dtarget within the required margins by the above explained feed forward strategy, since the values of Dinitial may exhibit a significant variance and the process may be subjected to systematic drifts over time, thereby rendering the conventional control strategy inefficient and thus significantly reducing the yield of the production process.
In view of this situation, there exists a need for an improved technique that enables the control of a critical dimension of a circuit element, such as a gate electrode, with an enhanced accuracy even if dimensions are further scaled.